Cell scaling is of critical importance to continued improvement of complementary metal-oxide-semiconductor (CMOS) technology. A VFET is a promising device to enable device scaling beyond the 5 nm technology node. As a result, new constructs are required to allow continued scaling—moving to a vertical architecture in particular allows the use of new interconnect constructs that should allow continued scaling. Unlike a traditional six transistor (6T), an eight transistor (8T) dual port SRAM circuit has two more transistors, which decouple the READ function such that the READ and WRITE memory functions can be performed simultaneously.
Traditionally, to perform a SRAM READ function, a high voltage is applied to a SRAM word line (WL) and a bitline/bitline-bar (BL/BLB) is pre-charged to a high voltage; the success of which may be determined by sensing the voltage difference between the BL and the BLB. SRAM cell stability requires a cell to retain original data after the READ function, which has a strong correlation to a beta ratio (on current (Ion) of a pull-down (PD) transistor divided by the Ion of a pass gate (PG) transistor (Ion_PD/Ion_PG)). In contrast, to perform a SRAM WRITE function, a high voltage is applied to a WL and a BL/BLB is pre-charged to a data value; the success of which equals the ability to flip a bitcell internal node according to the WRITE data. Consequently, writability equals a strong correlation to a gamma ratio (Ion_PG divided by the Ion of a pull-up (PU) gate (Ion_PG/Ion_PU)). As a result, cell stability (beta ratio) and cell writability (gamma ratio) generate conflicting requirements on PG Ion.
A need therefore exists for methodology enabling a balance between conflicting requirements on PG Ion for cell stability and cell writability to achieve an improved soft yield (Ysoft) relative to a traditional SRAM and the resulting device.